A hardware overview of the RHIC LLRF platform

The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. OVERVIEW The RHIC LLRF platform was designed with the intention of being used for all LLRF systems in the BNL Collider Accelerator complex. Thus, flexibility and scalability were key design considerations which led to the modular concept. The central piece of hardware is a carrier board which serves as an FEC and has six XMC daughter sites to implement specific RF system functions. The carrier is mounted in a chassis with power supplies and numerous support boards to form an RF Controller (see figure1). Four fiber optic data links on the carrier allow multiple RF Controllers to be connected to form a distributed system. System specific functionality is implemented using custom designed XMC daughter cards. The XMC standard allows the use of commercial XMC boards in the system if necessary. In order to enhance flexibility, both the carrier and daughter designs are centered around large FPGAs. Both have large banks of memory to permit acquiring substantial blocks of diagnostic data. Maximum design reuse was employed to optimize limited hardware engineering resources. Another benefit of this is that much of the embedded firmware in the FPGAs can also be re-used [1].