DESIGN OF HIGH SPEED AREA OPTIMIZED BINARY CODED DECIMAL DIGIT ADDER

Decimal arithmetic is necessary for computations in the field of banking systems,tax calculations,telephone billings etc. The main problem in the prevailing decimal arithmetic is the requirement of the correction of the result in its binary form. This results in larger area and implementation delay. The proposed adder is improved for less delay and area requirement as a correction free mechanism provides the result without adding any correction values.