A new construction adder based on Chinese abacus algorithm

A new construction adder based on Chinese abacus algorithm is presented in this paper. There are two kinds of beads used in this construction. Each column element has three higher beads with a weight of four and three lower beads with a weight of one. The proposed 32-bit adder contains eight column elements. The construction was simulated by the technology of TSMC [email protected] CMOS process. Layout was also made by the same technology. The maximum delay of the 32-bit abacus adder is 0.91ns and 14% less than that of Carry Look-ahead Adders for [email protected] technology. The power consumption of the abacus adder is 3.1mW and 28% less than that of Carry Look-ahead Adders for [email protected] technology. Recent researches are compared with the proposed adder. The construction was also simulated by Predictive Technology Model. The PTM results also presented. The use of Chinese abacus approach offers a competitive technique with respect to other adders.

[1]  M. Othman,et al.  High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm , 2006, 2006 IEEE International Conference on Semiconductor Electronics.

[2]  Mitchell A. Thornton,et al.  A signed binary addition circuit based on an alternative class of addition tables , 2003, Comput. Electr. Eng..

[3]  Pramod Kumar Meher,et al.  Area-efficient parallel-prefix Ling adders , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[4]  A Papachristou Christos.  Iterative construction of binary lookahead addition trees , 1986 .

[5]  Chen Gang,et al.  The Chinese Abacus method: can we use it for digital arithmetic? , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[6]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[7]  Franco Maloberti,et al.  Use of the Chinese Abacus method for digital arithmetic functions , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[8]  Eby G. Friedman,et al.  Tapered transmission gate chains for improved carry propagation [arithmetic logic circuits] , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[9]  Chenn-Jung Huang,et al.  A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic , 2003 .

[10]  Chen Gang,et al.  Performing arithmetic functions with the Chinese abacus approach , 1999 .

[11]  J. A. Gibson,et al.  Hybrid serial-parallel digital computation , 1980 .

[12]  Erdal Oruklu,et al.  Constant addition with flagged binary adder architectures , 2010, Integr..

[13]  Dimitrios Soudris,et al.  Designing low-power energy recovery adders based on pass transistor logic , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[14]  Mao Zhi-gang,et al.  A high speed 0.25 /spl mu/m 64-bit CMOS adder design , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[15]  Sung-Mo Kang,et al.  A 32-bit carry lookahead adder using dual-path all-N logic , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Ghassem Jaberipur,et al.  An improved maximally redundant signed digit adder , 2010, Comput. Electr. Eng..