A 3 Gb/s transmitter with a tapless pre-emphasis CML output driver

Abstract A 3 Gb/s wireline transmitter (Tx) with a tapless pre-emphasis current-mode logic output driver is presented in this paper. The proposed output driver can support 2.5, 6 and 10 dB pre-emphasis without any additional current tap. It can reduce the current consumption of the output driver by 30 %. The 1.5 GHz phase-locked loop (PLL), multi-phase generator, and 26-to-1 serializer are utilized to serialize 26-bit parallel data to 1-bit 3 Gb/s serial data stream. The rms and peak-to-peak jitters of PLL are 2.97 and 22.5 ps, respectively. The eye opening of the proposed output driver at 3 Gb/s is 0.8UI with a 10 dB loss channel. The current consumption of the output driver is only 5.14 mA, and the Tx is 9 mA. The area of the Tx is 0.72 mm2 using the 0.11 μm CMOS process.

[1]  Shyh-Jye Jou,et al.  4/2 PAM Pre-emphasis Transmitter with Combined Driver and Mux , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[2]  Eric A. M. Klumperink,et al.  Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS , 2006, VLSIC 2006.

[3]  B. Nauta,et al.  Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-/spl mu/m CMOS , 2006, IEEE Journal of Solid-State Circuits.

[4]  Dianyong Chen,et al.  A reduced power 6-tap pre-emphasis for 10GB/S backplane communications , 2008, 2008 24th Biennial Symposium on Communications.

[5]  Shen-Iuan Liu,et al.  A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Jae-Yoon Sim,et al.  A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[7]  Wenjie Huang,et al.  A 0.18 /spl mu/m CMOS transceiver design for high-speed backplane data communications , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[8]  Anthony Chan Carusone,et al.  A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[9]  A. Rylyakov,et al.  A low power 10 Gb/s serial link transmitter in 90-nm CMOS , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..