A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs
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[1] Melvin S. George,et al. Incorporating weighted round robin in honeybee algorithm for enhanced load balancing in cloud environment , 2017, 2017 International Conference on Communication and Signal Processing (ICCSP).
[2] Bertrand Granado,et al. Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).
[3] Fernanda Gusmão de Lima Kastensmidt,et al. Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs , 2019, 2019 IEEE Latin American Test Symposium (LATS).
[4] Lei He,et al. IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[5] Michael J. Wirthlin,et al. Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs , 2017, IEEE Transactions on Nuclear Science.
[6] Gabriel L. Nazar,et al. Exploring redundancy granularities to repair real-time FPGA-based systems , 2017, Microprocess. Microsystems.
[7] S. Katkoori,et al. Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.
[8] Giuliano Casale,et al. Evaluating Weighted Round Robin Load Balancing for Cloud Web Services , 2014, 2014 16th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing.
[9] Gabriel L. Nazar,et al. Accelerated FPGA repair through shifted scrubbing , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.
[10] Hyunok Oh,et al. Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening , 2015, IEEE Transactions on Computers.
[11] Marco D. Santambrogio,et al. SEU mitigation for sram-based fpgas through dynamic partial reconfiguration , 2007, GLSVLSI '07.
[12] Amlan Chakrabarti,et al. A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code , 2016, IEEE Embedded Systems Letters.
[13] Sadiq M. Sait,et al. A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] Mehdi Baradaran Tahoori,et al. Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] Yu Peng,et al. SRAM FPGAs single event upsets detection method based on selective readback , 2017, Prognostics and System Health Management Conference.
[16] Michael J. Wirthlin,et al. A Hybrid Approach to FPGA Configuration Scrubbing , 2017, IEEE Transactions on Nuclear Science.
[17] Fabio Benevenuti,et al. Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA , 2019, IEEE Transactions on Nuclear Science.
[18] John P. Hayes,et al. Enhancing design robustness with reliability-aware resynthesis and logic simulation , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[19] Christos-Savvas Bouganis,et al. Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs , 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).
[20] Shi-Jie Wen,et al. Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.
[21] M. Alderighi,et al. Comparison of the Susceptibility to Soft Errors of SRAM-Based FPGA Error Correction Codes Implementations , 2012, IEEE Transactions on Nuclear Science.
[22] Mehdi Baradaran Tahoori,et al. Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] He Chen,et al. An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC , 2018, 2018 International Conference on Field-Programmable Technology (FPT).
[24] Huiyun Li,et al. An Error Location and Correction Method for Memory Based on Data Similarity Analysis , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[25] Guanghui He,et al. A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).
[26] Keshab K. Parhi,et al. Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR) , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).
[27] Gabriel L. Nazar,et al. Fine-Grained Fast Field-Programmable Gate Array Scrubbing , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[28] Xiaoxuan She,et al. Reducing Critical Configuration Bits via Partial TMR for SEU Mitigation in FPGAs , 2017, IEEE Transactions on Nuclear Science.
[29] M. Lopez-Vallejo,et al. System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers , 2014, IEEE Transactions on Nuclear Science.
[30] R. Biswas,et al. Finding Time Quantum of Round Robin CPU Scheduling Algorithm Using Fuzzy Logic , 2008, 2008 International Conference on Computer and Electrical Engineering.
[31] Matteo Sonza Reorda,et al. An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems , 2017, IEEE Transactions on Computers.
[32] Yizhuang Xie,et al. FPGA-based fault injection design for 16K-point FFT processor , 2019 .
[33] L. Sterpone,et al. An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs , 2006, IEEE Transactions on Nuclear Science.
[34] Raffaele Giordano,et al. Redundant-Configuration Scrubbing of SRAM-Based FPGAs , 2017, IEEE Transactions on Nuclear Science.
[35] Yan Li,et al. Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[36] Michael Nicolaidis,et al. Embedded robustness IPs for transient-error-free ICs , 2002, IEEE Design & Test of Computers.
[37] David D. Yao,et al. Optimal load balancing and scheduling in a distributed computer system , 1991, JACM.