An analytical charge-based compact delay model for submicrometer CMOS inverters

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-/spl mu/m and a 0.35-/spl mu/m process technologies show significant improvements over previous models.

[1]  Jaume Segura,et al.  Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Takayasu Sakurai,et al.  A simple MOSFET model for circuit analysis , 1991 .

[3]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[4]  J. Meyer.  MOS models and circuit simulations , 1971 .

[5]  W. Shockley,et al.  A Unipolar "Field-Effect" Transistor , 1952, Proceedings of the IRE.

[6]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[7]  Daniel P. Foty,et al.  MOSFET Modeling With SPICE: Principles and Practice , 1996 .

[8]  Jaume Segura,et al.  Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis , 2002 .

[9]  Spiridon Nikolaidis,et al.  Propagation delay and short-circuit power dissipation modeling of the CMOS inverter , 1998 .

[10]  Maurizio Zamboni,et al.  A comprehensive submicrometer MOST delay model and its application to CMOS buffers , 1997 .

[11]  D. Auvergne,et al.  A comprehensive delay macro modeling for submicrometer CMOS logics , 1999, IEEE J. Solid State Circuits.

[12]  Spiridon Nikolaidis,et al.  Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices , 1998, IEEE J. Solid State Circuits.

[13]  Takayasu Sakurai,et al.  Delay analysis of series-connected MOSFET circuits , 1991 .

[14]  Kjell Jeppson,et al.  Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay , 1994 .

[15]  Asim J. Al-Khalili,et al.  Technology portable analytical model for DSM CMOS inverter transition time estimation , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[16]  K. Tamura,et al.  Estimation of Propagation Delay considering Short-Circuit Current for Static CMOS Gates , 1998 .