A Low-power and Compact AES S-box IP in 0.25μm CMOS for Wireless Sensor Network

Exploiting composite field arithmetic in Galois field is the common strategy to implement compact S-box. The power consumption of the composite field S-box, however, is too large to be used in wireless sensor network, where both power and area are critical. To find a low-power and compact S-box circuit for targeted applications, a full-custom hardware implementation of asynchronous circuit architecture over composite field is proposed. The pass transmission gates logic is used to realize the functionality of S-box. The low-power latches controlled by the new asynchronous component are inserted in the data processing circuit to eliminate the influence of the dynamic hazards. The resulting circuit can be a hardware Intelligent Property embedded in the wireless sensor node chips, since it dissipates low power consumption and still possesses the compact advantage of the composite field S-box.

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