Implementation of DVB-RCS turbo decoder for satellite on-board processing

The objective of the present paper is to provide a description of a turbo decoding algorithm for turbo codes standardised for DVB-RCS. It also presents the associated design architecture implemented in very high speed integrated circuit hardware description language (VHDL), as well as synthesis on a specific field programmable gate array (FPGA). The decoding structure was tested using a rapid prototyping system based on high-density Xilinx FPGAs.