A 0.010mm 2 9.92psrms Low Tracking Jitter Pixel Clock Generator with a Divider Initializer and a Nearest Phase Selector in 28nm

A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured tracking jitter is 9.92psrms. The total power consumption is 9.7mW and the silicon area is only 0.010mm 2 in 28nm CMOS process.