ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications
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Bo Zhang | Ming Qiao | Zhaoji Li | Lingli Jiang | Hang Fan | Bo Zhang | Zhaoji Li | M. Qiao | Lingli Jiang | Hang Fan
[1] Dong Sung Ma,et al. High-voltage power integrated circuit technology using SOI for driving plasma display panels , 2001 .
[2] H. Wolf,et al. Impact of layer thickness variations of SOI-wafer on ESD-robustness , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.
[3] S. Voldman. ESD: Physics and Devices , 2004 .
[4] Ming-Dou Ker,et al. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs , 2005 .
[5] Ming-Dou Ker,et al. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs , 2005, IEEE Journal of Solid-State Circuits.
[6] Steven H. Voldman. A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup , 2005, Microelectron. Reliab..
[7] Weifeng Sun,et al. High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC , 2006 .
[8] H. Kobayashi,et al. 250V-Class Lateral SOI Devices for Driving HDTV PDPs , 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.
[9] Zhiwei Liu,et al. Novel Silicon-Controlled Rectifier (SCR) for High-Voltage Electrostatic Discharge (ESD) Applications , 2008, IEEE Electron Device Letters.
[10] G. Meneghesso,et al. Novel 190V LIGBT-based ESD protection for 0.35μm Smart Power technology realized on SOI substrate , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.
[11] H. Gossner,et al. Transient behavior of SCRS during ESD pulses , 2008, 2008 IEEE International Reliability Physics Symposium.
[12] P. Wambacq,et al. A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA , 2009, IEEE Journal of Solid-State Circuits.
[13] V.A. Vashchenko,et al. System level and hot plug-in protection of high voltage transient pins , 2009, 2009 31st EOS/ESD Symposium.
[14] Ming-Dou Ker,et al. New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS , 2010, IEEE Electron Device Letters.
[15] Chun-Yu Lin,et al. Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies , 2011, IEEE Transactions on Device and Materials Reliability.
[16] Weifeng Sun,et al. The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection , 2012, IEEE Transactions on Device and Materials Reliability.
[17] Yan Han,et al. Investigation of ESD protection strategy in high voltage Bipolar-CMOS-DMOS process , 2012, Microelectron. Reliab..