Motion estimation processor using mixed-signal approach

This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-mum CMOS technology occupying 0.65 mm2, and operates on 4 times 4 pixel blocks and a search area of 8 times 8 pixels. The processor achieves a low energy consumption per motion vector of 1.35 nJ and dissipates 0.8 mW from a 3-V power supply at QCIF 15 frames/s. The approach is intended for portable applications of digital video encoding

[1]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[2]  Asad A. Abidi,et al.  An 8 b CMOS vector A/D converter , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Andreas Demosthenous,et al.  A compact block-matching cell for analogue motion estimation processors , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Peter Kuhn,et al.  Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation , 1999, Springer US.

[5]  Masahiko Yoshimoto,et al.  A sub-mW MPEG-4 motion estimation processor core for mobile video application , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[6]  Mladen Panovic.  Analogue implementation of motion estimation processors for digital video coding , 2005 .

[7]  Thou-Ho Chen.  A cost-effective three-step hierarchical search block-matching chip for motion estimation , 1998 .

[8]  Michael Mills,et al.  Blockmatching motion estimation algorithms-new results , 1990 .

[9]  M. Pasotti,et al.  B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[10]  Shengqi Yang,et al.  Power and performance analysis of motion estimation based on hardware and software realizations , 2005, IEEE Transactions on Computers.

[11]  Ming-Jer Chen,et al.  A compact high-speed Miller-capacitance-based sample-and-hold circuit , 1998 .

[12]  G. Cauwenberghs,et al.  A low-power CMOS analog vector quantizer , 1997 .

[13]  A. Demosthenous,et al.  A low-power analog motion estimation processor for digital video coding , 2006, IEEE Journal of Solid-State Circuits.

[14]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[15]  Roberto Guerrieri,et al.  A Low-Power Block-Matching Cell for Video Compression , 2001 .

[16]  R. Zafalon,et al.  Ultra low-power multimedia processor for mobile multimedia applications , 2002, Proceedings of the 28th European Solid-State Circuits Conference.