Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing the number of signals traced and maximizing the observability/restorability of other untraced signals during post-silicon validation. This paper presents a new method for trace buffer signal selection for the purpose of post-silicon debug. The selection is performed by favoring those signals with the most number of implications that are not implied by other signals. Then, based on the values of the traced signals during silicon debug, we introduce an algorithm which uses a SAT-based multi-node implication engine to restore the values of untraced signals across multiple time-frames. Experimental results for sequential benchmark circuits showed that the proposed approach selects the trace signals effectively, giving a high restoration percentage compared with other techniques.

[1]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Harry Siebert,et al.  Boosting Debugging Support for Complex Systems on Chip , 2007, Computer.

[3]  R. Leatherman,et al.  An embedding debugging architecture for SOCs , 2005, IEEE Potentials.

[4]  Mack W. Riley,et al.  Cell Broadband Engine Debugging for Unknown Events , 2007, IEEE Design & Test of Computers.

[5]  Janak H. Patel,et al.  A graph traversal based framework for sequential logic implication with an application to C-cycle redundancy identification , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[6]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Peter Dahlgren,et al.  Latch divergency in microprocessor failure analysis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[8]  Michael S. Hsiao,et al.  Using Scan-Dump Values to Improve Functional-Diagnosis Methodology , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[9]  Nicola Nicolici,et al.  Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Nicola Nicolici,et al.  Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs , 2008, 2008 IEEE International Test Conference.

[11]  Nicola Nicolici,et al.  On using lossless compression of debug data in embedded logic analysis , 2007, 2007 IEEE International Test Conference.

[12]  Martin Burtscher,et al.  The VPC trace-compression algorithms , 2005, IEEE Transactions on Computers.

[13]  Ismet Bayraktaroglu,et al.  Microprocessor silicon debug based on failure propagation tracing , 2005, IEEE International Conference on Test, 2005..

[14]  Nicola Nicolici,et al.  Low Cost Debug Architecture using Lossy Compression for Silicon Debug , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.