Performance directed synthesis for table look up programmable gate arrays
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Robert K. Brayton | Alberto L. Sangiovanni-Vincentelli | Rajeev Murgai | Narendra V. Shenoy | R. Brayton | A. Sangiovanni-Vincentelli | N. Shenoy | R. Murgai
[1] Robert K. Brayton,et al. Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[2] Richard M. Karp,et al. Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..
[3] Mark Horowitz,et al. Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Robert K. Brayton,et al. Logic synthesis for programmable gate arrays , 1991, DAC '90.
[5] Massoud Pedram,et al. Layout driven technology mapping , 1991, 28th ACM/IEEE Design Automation Conference.
[6] Robert K. Brayton,et al. Performance-oriented technology mapping , 1990 .
[7] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Rajeev Murgai,et al. Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[9] Jonathan Rose,et al. Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.