Multicycle Broadside and Skewed-Load Tests for Test Compaction

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits.

[1]  Edward J. McCluskey,et al.  Launch-on-Shift-Capture Transition Tests , 2008, 2008 IEEE International Test Conference.

[2]  Irith Pomeranz.  Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Irith Pomeranz,et al.  Static test compaction for delay fault test sets consisting of broadside and skewed-load tests , 2011, 29th VLSI Test Symposium.

[4]  Sudhakar M. Reddy,et al.  Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

[5]  Irith Pomeranz.  Generation of Multi-Cycle Broadside Tests , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Hiroshi Takahashi,et al.  Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

[7]  Sudhakar M. Reddy,et al.  At-speed scan test with low switching activity , 2010, 2010 28th VLSI Test Symposium (VTS).

[8]  Srinivas Patil,et al.  Scan-based transition test , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Seiji Kajihara,et al.  Multi-cycle Test with Partial Observation on Scan-Based BIST Structure , 2011, 2011 Asian Test Symposium.

[10]  Xijiang Lin,et al.  Test generation for designs with multiple clocks , 2003, DAC '03.

[11]  Irith Pomeranz.  A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Irith Pomeranz,et al.  Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Jeff Rearick.  Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[14]  Adit D. Singh,et al.  Scan cell design for launch-on-shift delay tests with slow scan enable , 2007, IET Comput. Digit. Tech..

[15]  Irith Pomeranz,et al.  Static test compaction for scan-based designs to reduce test application time , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[16]  C. P. Ravikumar,et al.  Local at-speed scan enable generation for transition fault testing using low-cost testers , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Kewal K. Saluja,et al.  Test application time reduction for sequential circuits with scan , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  James Sage,et al.  Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns , 2007, 2007 IEEE International Test Conference.

[19]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..