ESD protection for advanced CMOS SOI technologies

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.

[1]  P. Mortini,et al.  Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[2]  Elyse Rosenbaum,et al.  EOS/ESD reliability of partially depleted SOI technology , 1999 .

[3]  M. Stockinger,et al.  Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies , 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

[4]  P.A. Juliano,et al.  ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[5]  E. Rosenbaum,et al.  Time-dependent snapback in thin-film SOI MOSFET's , 1997, IEEE Electron Device Letters.

[6]  S. S. Yuen,et al.  Comparison of ESD protection capability of SOI and bulk CMOS output buffers , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[7]  Cynthia A. Torres,et al.  Advanced rail clamp networks for ESD protection , 2005, Microelectron. Reliab..

[8]  N. Subba,et al.  ESD protection for SOI technology using an under-the-box (substrate) diode structure , 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

[9]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[10]  A. Amerasekera,et al.  Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[11]  M. Stockinger,et al.  Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[12]  Sung-Mo Kang,et al.  EOS/ESD protection circuit design for deep submicron SOI technology , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[13]  P. Mortini,et al.  Investigation on different ESD protection strategies devoted to 3.3V RF applications (2GHz) in a 0.18μm CMOS process , 2002 .

[14]  Cynthia A. Torres,et al.  Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[15]  R. Gauthier,et al.  Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[16]  Elyse Rosenbaum,et al.  Prediction of ESD protection levels and novel protection devices in thin film SOI technology , 1997 .

[17]  D. Hui,et al.  Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[18]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[19]  M. Sherony,et al.  Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[20]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[21]  S. Ramaswamy,et al.  Heat flow analysis for EOS/ESD protection device design in SOI technology , 1997 .

[22]  J.W. Miller,et al.  Engineering the cascoded NMOS output buffer for maximum V/sub t1/ , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[23]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.