Design of Ultra-Low-Voltage Energy Efficient Hybrid Full Adder Circuit

In recent years, ultra-low-voltage (ULV) operation is gaining more importance to achieve minimum energy consumption. This chapter aims at minimizing the energy consumption of the full adder circuits in the near threshold region of operation. A new hybrid full adder circuit which employs CMOS logic and transmission gate (TG) logic with dynamic threshold MOS (DTMOS) scheme is presented. The DTMOS is one of the body bias schemes used to improve the performance in ULV operation by dynamically varying the threshold voltage of the transistors. The performance metrics—energy, power, delay and EDP are calculated and compared with the conventional CMOS full adder. The simulations are performed using Cadence 90 nm technology with ultra-low-voltage of 0.2 V (subthreshold region). The results have shown that the proposed hybrid full adder circuit with DTMOS scheme achieves more than 26% savings in delay, 15% savings in energy consumption and 38% savings in EDP in comparison with the static CMOS configuration.

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