Reconfiguration Strategies for Parallel Architectures

Communication paths between parallelarchitecture resources can be reconfigured to suit new computational structures; however, this capability places new demands on efficient architecture use. In the past decade a significant amount of research focused on the development of highly parallel architectures.' Progress in research on Very-Large-Scale-Integrated-Circuit (VLSI) and Very-High-Speed-Integrated-Circuit (VHSIC) technologies is making it feasible to consider the construction ofcomplex parallel architectures that comprise a number of processors communicating by means of a high-bandwidth interconnection network. (Two often-proposed organizations, the processor-memory and the processor-processor network, are shown in Figure 1.) By utilizing a large number of such processors, these architectures have the potential to provide enormous throughputs leading to the computation of processes previously considered impractical due to their complexity. However, the availability of multiple processors alone is not sufficient to ensure practical solutions to computationally intensive tasks. One of several modes of operation may be de-

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