A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.

[1]  Shyue-Win Wei,et al.  VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/) , 1997 .

[2]  Hanho Lee.  High-speed VLSI architecture for parallel Reed-Solomon decoder , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  Luca Crippa,et al.  A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[4]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[5]  D. Strukov,et al.  The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[6]  Guido Torelli,et al.  On-chip error correcting techniques for new-generation flash memories , 2003, Proc. IEEE.

[7]  G. Torelli,et al.  40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory , 2000, IEEE Journal of Solid-State Circuits.

[8]  Shyue-Win Wei,et al.  A high-speed real-time binary BCH decoder , 1993, IEEE Trans. Circuits Syst. Video Technol..

[9]  Daniele Vimercati,et al.  A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface , 2008, IEEE Journal of Solid-State Circuits.