Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors

Application Specific Programmable Processors (ASPP) provide efficient implementation for any of m specified functionalities. Due to their flexibility and convenient performance-cost trade-offs, ASPPs are being developed by DSP, video, multimedia, and embedded lC manufacturers. In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs. ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis: Graceful degradation is supported by implementing multiple schedules of the ASPP applications, each with a different throughput constraint. In this paper, we do not consider concurrent error detection. The first ASPP fault tolerance technique minimizes the hardware resources while guaranteeing that the ASPP remains operational in the presence of all k-unit faults. On the other hand, the second fault tolerance technique maximizes the ASPP fault tolerance subject to constraints on the hardware resources. These ASPP fault tolerance techniques impose several unique tasks, such as fault-tolerant scheduling, hardware allocation, and application-to-faulty-unit assignment. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.

[1]  MalikSharad,et al.  Power analysis and minimization techniques for embedded DSP software , 1997 .

[2]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[3]  Hoon Choi,et al.  Synthesis of application specific instructions for embedded DSP software , 1998, ICCAD '98.

[4]  G.D. Hillman DSP56200: An algorithm-specific digital signal processor peripheral , 1987, Proceedings of the IEEE.

[5]  Ramesh Karri,et al.  Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Rainer Leupers,et al.  Retargetable assembly code generation by bootstrapping , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[7]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[9]  S. S. Ravi,et al.  Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[10]  Miodrag Potkonjak,et al.  Heterogeneous built-in resiliency of application specific programmable processors , 1996, ICCAD 1996.

[11]  Brad L. Hutchings,et al.  Design methodologies for partially reconfigured systems , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[12]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[13]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[14]  Miodrag Potkonjak,et al.  Synthesis of application specific programmable processors , 1997, DAC.

[15]  Glenn H. Chapman,et al.  A wafer-scale digital integrator using restructurable VSLI , 1985 .

[16]  Chong-Min Kyung,et al.  Synthesis of Application Specific Instructions for Embedded DSP Software , 1999, IEEE Trans. Computers.

[17]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[18]  Douglas M. Blough,et al.  Optimal recovery point insertion for high-level synthesis of recoverable microarchitectures , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[19]  Pierre G. Paulin,et al.  CodeSyn: a retargetable code synthesis system (abstract) , 1994, ISSS '94.

[20]  Miodrag Potkonjak,et al.  Maximizing the fault-tolerance of application specific programmable signal processors , 1996, VLSI Signal Processing, IX.

[21]  C. C. Stearns,et al.  A reconfigurable 64-tap transversal filter , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[22]  Israel Koren,et al.  Phantom redundancy: a high-level synthesis approach for manufacturability , 1995, ICCAD.

[23]  Mariagiovanna Sami,et al.  Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays , 1989 .

[24]  Satoshi Kaneko,et al.  Defect and fault tolerance FPGAs by shifting the configuration data , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[25]  Miodrag Potkonjak,et al.  High level synthesis techniques for efficient built-in-self-repair , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[26]  Sharad Malik,et al.  Static timing analysis of embedded software , 1997, DAC.

[27]  Pierre G. Paulin,et al.  CodeSyn : A Retargetable Code Synthesis System , 1997 .

[28]  André DeHon,et al.  DPGA-coupled microprocessors: commodity ICs for the early 21st Century , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[29]  Ramesh Karri,et al.  Phantom redundancy: a high-level synthesis approach for manufacturability , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[30]  Niraj K. Jha,et al.  Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[31]  Shantanu Dutt,et al.  Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[32]  Edward A. Lee,et al.  Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.

[33]  M. Potkonjak,et al.  Synthesis Of Application Specific Programmable Processors , 1997, Proceedings of the 34th Design Automation Conference.

[34]  Fabrizio Lombardi,et al.  Fault tolerance of one-time programmable FPGAs with faulty routing resources , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.

[35]  J. M. Rabaey,et al.  A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[36]  Hugo De Man,et al.  Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures , 1995, J. VLSI Signal Process..

[37]  Miodrag Potkonjak,et al.  Low overhead fault-tolerant FPGA systems , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[38]  Ramesh Karri,et al.  Automatic Synthesis of Self-Recovering VLSI Systems , 1996, IEEE Trans. Computers.

[39]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[40]  Vincenzo Piuri,et al.  High-level synthesis of data paths with concurrent error detection , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[41]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[42]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[43]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[44]  P.W. Wyatt,et al.  A Wafer-Scale Digital Integrator Using Restructurable VSLI , 1985, IEEE Journal of Solid-State Circuits.

[45]  John Paul Shen,et al.  Architecture synthesis of high-performance application-specific processors , 1991, DAC '90.

[46]  Ramesh Karri,et al.  Optimal self-recovering microarchitecture synthesis , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[47]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[48]  Brad L. Hutchings,et al.  Supporting FPGA microprocessors through retargetable software tools , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.