Placement and Routing for Performance-Oriented FPGA Layout
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Joseph L. Ganley | James P. Cohoon | Gabriel Robins | Michael J. Alexander | J. L. Ganley | G. Robins | J. Cohoon | M. J. Alexander
[1] Andrew B. Kahng,et al. A new class of iterative Steiner tree heuristics with good performance , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Joseph L. Ganley,et al. The Multi-Weighted Spanning Tree Problem , 1995 .
[3] Dana S. Richards,et al. Optimal two-terminal α-β wire routing , 1986, Integr..
[4] W.C. Collier,et al. Smart cars, smart highways , 1994, IEEE Spectrum.
[5] Jonathan Rose,et al. A detailed router for field-programmable gate arrays , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[6] James P. Cohoon,et al. A Parallel VLSI Circuit Layout Methodology , 1993, The Sixth International Conference on VLSI Design.
[7] Malgorzata Marek-Sadowska,et al. Graph based analysis of FPGA routing , 1993, EURO-DAC.
[8] Jason Cong,et al. Placement and placement driven technology mapping for FPGA synthesis , 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.
[9] Allen C.-H. Wu,et al. A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, 32nd Design Automation Conference.
[10] Steven Trimberger. Effects of FPGA Architecture on FPGA Routing , 1995, 32nd Design Automation Conference.
[11] Malgorzata Marek-Sadowska,et al. An efficient router for 2-D field programmable gate array , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[12] Martine D. F. Schlag,et al. On Routability Prediction for Field-Programmable Gate Arrays , 1993, 30th ACM/IEEE Design Automation Conference.
[13] Dwight D. Hill,et al. Routable technology mapping for LUT FPGAs , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[14] Joseph L. Ganley,et al. Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[15] Guy G.F. Lemieux. A Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays , 1998 .
[16] Joseph L. Ganley,et al. Performance-oriented placement and routing for field-programmable gate arrays , 1995, Proceedings of EURO-DAC. European Design Automation Conference.
[17] A. Kahng,et al. On optimal interconnections for VLSI , 1994 .
[18] Alberto L. Sangiovanni-Vincentelli,et al. A Detailed Router Based on Incremental Routing Modifications: Mighty , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Willy M. C. Sansen,et al. A Line-Expansion Algorithm for the General Routing Problem with a Guaranteed Solution , 1980, 17th Design Automation Conference.
[20] Pierre Marchal,et al. Field-programmable gate arrays , 1999, CACM.
[21] Joseph L. Ganley,et al. An architecture-independent approach to FPGA routing based on multi-weighted graphs , 1994, EURO-DAC '94.
[22] Jason Cong,et al. DAG-Map: graph-based FPGA technology mapping for delay optimization , 1992, IEEE Design & Test of Computers.
[23] Gabriel Robins,et al. New Performance-Driven FPGA Routing Algorithms , 1996, 32nd Design Automation Conference.
[24] Jon Frankle,et al. Iterative and adaptive slack allocation for performance-driven layout and FPGA routing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[25] A. El Gamal,et al. An architecture for electrically configurable gate arrays , 1989 .
[26] Jeffrey S. Salowe,et al. Closing the gap: near-optimal Steiner trees in polynomial time , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Kevin Karplus. Xmap: a technology mapper for table-lookup field-programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.
[28] M. R. Rao,et al. Combinatorial Optimization , 1992, NATO ASI Series.
[29] J. L. Ganley. Geometric interconnection and placement algorithms , 1995 .
[30] Brian W. Kernighan,et al. A Procedure for Placement of Standard-Cell VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[31] Kurt Antreich,et al. PHIroute: A parallel hierarchical sea-of-gates router , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[32] William J. Cook,et al. Combinatorial optimization , 1997 .
[33] Catherine A. Schevon,et al. Optimization by simulated annealing: An experimental evaluation , 1984 .
[34] C. D. Gelatt,et al. Optimization by Simulated Annealing , 1983, Science.