Efficient Design and Implementation of LTE Downlink Control Information Decoder

 Abstract—The decoding of Downlink Control Information (DCI) in LTE is based upon a process that is defined as a blind decoding which depends on a number of decoding attempts on a number of Physical Downlink Control Channel (PDCCH) candidate locations for a number of defined DCI formats. In this paper, two proposed designs for DCI decoder are presented. The first decodes based upon monitoring PDCCH candidate locations serially. This design can perform the whole 44 decoding attempts within 87.3 % of the whole OFDM symbol time with extended cyclic prefix. So, it's well suited for Multicast/Broadcast over Single Frequency Network (MBSFN) subframes. However, this design doesn't meet the worst-case time of an LTE OFDM symbol with normal cyclic prefix. Therefore, a second design is proposed that exploits parallelism to enable fast blind decoding process. The proposed parallel design proves efficiency in meeting decoding time constraints besides, consuming a little power with a proven efficiency in utilization area perspective. The proposed parallel design performs all of 44 decoding attempts in a time of 7.8 µs which is only 11.7 % of an LTE useful OFDM symbol time with a logic power consumption of only 17000 µW. The proposed designs are simulated using Modelsim 6.4a and implemented in Plan Ahead 14.4 in 28 nm technology, Virtex7 FPGA kit of part number XC7V2000T, which is characterized by high performance and large capacity.