Wave pipelining for application-specific networks-on-chips

This paper presents methods for optimizing application-specific networks-on-chips (NoCs). We show that wave pipelining provides more energy efficient data transport than non-wave pipelined communication. We observe 52% energy saving, 60% transistor area saving, and 1.7 times speedup by using wave pipelining in simulation. Wave pipelining is particularly well suited to networks-on-chips because the networkes structured interconnection provides better delay control. Our analysis shows how designers can tune their network to the requirements of the application by choosing a design point along area/performance or area/energy curves.

[1]  Luciano Lavagno,et al.  Formal Models for Communication-Based Design , 2000, CONCUR.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[3]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[4]  Sujit Dey,et al.  Evaluation of the traffic-performance characteristics of system-on-chip communication architectures , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[5]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[6]  Sorin A. Huss,et al.  VLSI system design using asynchronous wave pipelines: a 0.35 /spl mu/m CMOS 1.5 GHz elliptic curve public key cryptosystem chip , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[7]  Andrew B. Kahng,et al.  Interconnect tuning strategies for high-performance ICs , 1998, DATE.

[8]  W. Liu,et al.  Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Jin-Ku Kang,et al.  A self-timed wave pipelined adder using data align method , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[10]  Sachin S. Sapatnekar,et al.  Exact and efficient crosstalk estimation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Jason Cong,et al.  An interconnect-centric design flow for nanometer technologies , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[12]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[13]  Giovanni De Micheli,et al.  Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..