SEFOP: a novel approach to data path module placement

Tlria paper is concerned with utilizii rcgnhrity information of data path modules in placement and shows outstanding resnlts. Sindlarity Extraction is applied ftrst on a data path module given a set of slice nmnbcrs, a column nmnber, and IO pin ordering followed by a three-level Force-Oriented Placement for determining Aative locations of cells in the form of a cell matrix. Exact pin Iocatiom, cell tlipping, and rowlcolumn spacing are then estimated based on the cell placement. Experiments on cell-based designs demonstrate its performance over various general-purpose placement approaches at far less CPU time on data path rmdnle dcsigm.

[1]  Georg Sigl,et al.  GORDIAN: a new global optimization/rectangle dissection method for cell placement , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[2]  Carl Sechen,et al.  IMPROVED SIMULATED ANNEALING ALGORIHM FOR ROW-BASED PLACEMENT. , 1987 .

[3]  Wing K. Luk,et al.  Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  Gotaro Odawara,et al.  Partitioning and Placement Technique for CMOS Gate Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  M. Iachponi,et al.  A Hierarchical Gate Array Architecture and Design Methodology , 1985, 22nd ACM/IEEE Design Automation Conference.

[6]  Carl Sechen,et al.  Mickey: a macro cell global router , 1991, Proceedings of the European Conference on Design Automation..

[7]  Jason Cong Pin assignment with global routing , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Ernest S. Kuh,et al.  Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Chung-Kuan Cheng,et al.  Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Chong-Min Kyung,et al.  A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.