Towards a robust multi-antenna mass market GNSS receiver

An architecture concept for multi-antenna mass market GNSS receivers is presented. The architecture is composed of a central processing unit and attached coprocessors to solve the conflict between continuously increasing computational complexity of receiver algorithms and the demand for maximal receiver mobility (i.e. hardware featuring low cost and low energy consumption). To optimize navigation performance and robustness the presented receiver processing relies on the collected data in space, time, and frequency domain. Multi-antenna algorithms, e.g. interferer suppression, direction of arrival estimation, and tracking are briefly described. The basic hardware building blocks (coprocessors) required to efficiently realize these algorithms are introduced. Examples for the dimensioning of internal word length and block parameters are presented and first coprocessor implementations are shown. To reduce the costs of the overall receiver, synergistic effects should be exploited and the coprocessors should be used in a time multiplexed manner, where possible. Therefore, a first simple scheduling for the coprocessor access is shown. Finally, a platform for a real-time prototype realization of the presented architecture concept, on a state-of-the-art FPGA development board, is introduced. This paper proves that high performance multi-antenna GNSS receivers featuring interferer suppression as well as advanced signal processing and analysis can be realized using state-of-the-art FPGAs and thus shows a first step towards a mass market multi-antenna GNSS receiver.

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