Analysis of Several 2:1 Multiplexer Circuits at 90nm and 45nm Technologies
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Neha Arora | Ila Gupta | B. P. Singh | Ila Gupta | N. Arora | B. P. Singh
[1] S. Ramamurthy,et al. Low Power Digital VLSI Design Circuits and Systems , 2014 .
[2] Yasuhiko Sasaki,et al. Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.
[3] L. Heller,et al. Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] Kiseon Cho,et al. Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique , 2002, VLSI Design.
[5] Parag K. Lala,et al. A Fine Grain Configurable Logic Block for Self-checking FPGAs , 2001, VLSI Design.
[6] Shen-Fu Hsiao,et al. High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic , 2002, VLSI Design.
[7] Jan M. Rabaey,et al. Digital Integrated Circuits , 2003 .
[8] Shen-Fu Hsiao,et al. High-performance multiplexer-based logic synthesis using pass-transistor logic , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).