Application of logical effort on delay analysis of 64-bit static carry-lookahead adder

This paper presents the transistor-level analysis of the 64-bit static carry-lookahead adder (CLA). The carry blocks were implemented in two schemes: (A) 2-level and (B) multilevel. The logical effort technique was used to optimize the circuits for best performance. The analysis was verified with SPICE simulation, using 0.18 /spl mu/m, 1.8 V CMOS technology, and confirmed with small error. In addition, scheme B showed 12% improvement due to faster gate in carry block and less loading in (P,G) ones.

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