$GYDQFHG6HPLFRQGXFWRURQ,QVXODWR U6XEVWUDWHVIRU/RZ3RZHUDQG +LJK3HUIRUPDQFH'LJLWDO&026$SSOLFDWLRQV

It has become increasingly difficult to scale CMOS transistors beyond 130nm, yet still maintain high drive currents and reduce supply voltage (Vdd). Much attention has been focused on high mobility for boosting performance of the short channel devices. In this paper we will review the latest development in substrate engineering using the Smart Cut TM technique, new device architecture and challenges for III-V/Ge CMOS cointegration on the Si platform.

[1]  O. Faynot,et al.  Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length , 2005, 2005 IEEE International SOI Conference Proceedings.

[2]  S. Murphy,et al.  Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations. , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  M. Takenaka,et al.  III-V/Ge CMOS technologies on Si platform , 2010, 2010 Symposium on VLSI Technology.

[4]  P. Kirsch,et al.  Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow , 2010, 2010 International Electron Devices Meeting.

[5]  O. Faynot,et al.  25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[6]  S. Filipiak,et al.  1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..