Compiler-Assisted Leakage Energy Reduction for Cache Memories
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[1] Christer Svensson,et al. Trading speed for low power by choice of supply and threshold voltages , 1993 .
[2] Mahmut T. Kandemir,et al. Managing Leakage Energy in Cache Hierarchies , 2003, J. Instr. Level Parallelism.
[3] Gurindar S. Sohi,et al. A static power model for architects , 2000, MICRO 33.
[4] Kevin Skadron,et al. Adaptive Cache Decay using Formal Feedback Control , 2002 .
[5] Narayanan Vijaykrishnan,et al. Compiler optimizations for low power systems , 2002 .
[6] Wei Zhang. Compiler-directed data cache leakage reduction , 2004, IEEE Computer Society Annual Symposium on VLSI.
[7] Wei Zhang,et al. A compiler approach for reducing data cache energy , 2003, ICS '03.
[8] James R. Larus,et al. Branch prediction for free , 1993, PLDI '93.
[9] Wei Zhang,et al. Compiler support for reducing leakage energy consumption , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[10] Michel Cekleov,et al. Virtual-address caches. Part 1: problems and solutions in uniprocessors , 1997, IEEE Micro.
[11] Yan Meng,et al. Exploring the limits of leakage power reduction in caches , 2005, TACO.
[12] Vivek De,et al. A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[13] Trevor Mudge,et al. Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[14] Wei Zhang,et al. Compiler-directed instruction cache leakage optimization , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[15] Krste Asanovic,et al. Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.
[16] Lizy K. John,et al. Is Compiling for Performance — Compiling for Power? , 2001 .
[17] Ulrich Kremer,et al. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.
[18] Andrew Wolfe,et al. Compilation techniques for low energy: an overview , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.
[19] Chi-Ying Tsui,et al. Low power architecture design and compilation techniques for high-performance processors , 1994, Proceedings of COMPCON '94.
[20] Ulrich Kremer. Low-Power/Energy Compiler Optimizations , 2004 .
[21] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[22] Kaushik Roy,et al. Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[23] T. M. Conte,et al. Comparing software and hardware schemes for reducing the cost of branches , 1989, ISCA '89.
[24] Eric Rotenberg,et al. Adaptive mode control: a static-power-efficient cache design , 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.
[25] David Blaauw,et al. Gate oxide leakage current analysis and reduction for VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[26] Christian Piguet,et al. Low-Power Electronics Design , 2004 .
[27] Avi Mendelson,et al. Coming challenges in microarchitecture and architecture , 2001, Proc. IEEE.
[28] David Blaauw,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.
[29] Paolo Faraboschi,et al. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools , 2004 .
[30] B. Ramakrishna Rau,et al. Instruction-level Parallelism , 2001 .
[31] Mahmut T. Kandemir,et al. Exploiting program hotspots and code sequentiality for instruction cache leakage management , 2003, ISLPED '03.
[32] Rami Melhem,et al. Power Aware Computing , 2002, Series in Computer Science.
[33] Wei Zhang,et al. Static next sub-bank prediction for drowsy instruction cache , 2004, CASES '04.
[34] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.