Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce scan-based tests with one or more functional capture cycles between a scan-in and a scan-out operation. The approach to test generation referred to as transparent-scan has several advantages in this context. (1) It allows functional capture cycles and scan shift cycles to be interleaved arbitrarily. This increases the flexibility to assign to the scan cells values that are needed for diagnosis. (2) Test generation under transparent-scan considers a circuit model where the scan logic is included explicitly. Consequently, the test generation procedure takes into consideration the full effect of a scan chain fault. It thus produces accurate tests. (3) For the same reason, it can also target faults inside the scan logic. (4) Transparent-scan results in compact test sequences. Compaction is important because of the large volumes of fail data that scan chain faults create. The cost of transparent-scan is that it requires simulation procedures for sequential circuits, and that arbitrary sequences would be applicable to the scan select input. Motivated by the advantages of transparent-scan, and the importance of diagnosing scan chain faults, this article describes a procedure for generating transparent-scan sequences for diagnosis of scan chain faults. The procedure is also applied to produce transparent-scan sequences for diagnosis of faults inside the scan logic.

[1]  Mingjing Chen,et al.  Diagnosing scan chain timing faults through statistical feature analysis of scan images , 2011, 2011 Design, Automation & Test in Europe.

[2]  S. Narayanan,et al.  An efficient scheme to diagnose scan chains , 1997, Proceedings International Test Conference 1997.

[3]  Kwang-Ting Cheng,et al.  Diagnosing scan chains using SAT-based diagnostic pattern generation , 2007, 2007 IEEE International SOC Conference.

[4]  Chien-Mo James Li,et al.  Diagnosis of Multiple Scan Chain Timing Faults , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Wu-Tung Cheng,et al.  Diagnose Multiple Stuck-at Scan Chain Faults , 2008, 2008 13th European Test Symposium.

[6]  Yervant Zorian Embedding infrastructure IP for SOC yield improvement , 2002, DAC '02.

[7]  Erik Jan Marinissen,et al.  Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching , 2015, TODE.

[8]  TingTing Hwang,et al.  Utilizing Circuit Structure for Scan Chain Diagnosis , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Rohit Kapur,et al.  An ATE assisted DFD technique for Volume Diagnosis of scan chains , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  Alex Orailoglu,et al.  DiSC: A New Diagnosis Method for Multiple Scan Chain Failures , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Wu-Tung Cheng,et al.  A complete test set to diagnose scan chain failures , 2007, 2007 IEEE International Test Conference.

[12]  Yu Zhang,et al.  A diagnostic test generation system , 2010, 2010 IEEE International Test Conference.

[13]  Huajun Chen,et al.  A scan chain optimization method for diagnosis , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[14]  Yuejian Wu,et al.  Diagnosis of scan chain failures , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[15]  Andreas G. Veneris,et al.  Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG , 2005, J. Electron. Test..

[16]  Srikanth Venkataraman,et al.  A technique for fault diagnosis of defects in scan chains , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[17]  Y.-H. Chen,et al.  Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow , 2012, IET Comput. Digit. Tech..

[18]  Rohit Kapur,et al.  Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Paolo Prinetto,et al.  A diagnostic test pattern generation algorithm , 1990, Proceedings. International Test Conference 1990.

[20]  Paolo Prinetto,et al.  GARDA: a diagnostic ATPG for large synchronous sequential circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[21]  Sandip Kundu Diagnosing scan chain faults , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Edward J. McCluskey,et al.  Functional tests for scan chain latches , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[23]  Vishwani D. Agrawal,et al.  A Two Phase Approach for Minimal Diagnostic Test Set Generation , 2009, 2009 14th IEEE European Test Symposium.

[24]  Janusz Rajski,et al.  Diagnosis with Limited Failure Information , 2006, 2006 IEEE International Test Conference.

[25]  Ruifeng Guo,et al.  Diagnostic test generation for small delay defect diagnosis , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[26]  Chien-Mo James Li,et al.  Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis , 2006, 2006 IEEE International Test Conference.

[27]  Charles E. Stroud,et al.  Using embedded FPGAs for SoC yield improvement , 2002, DAC '02.

[28]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[29]  Vinita Vasudevan,et al.  An efficient algorithm for statistical timing yield optimization , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[30]  Sudhakar M. Reddy,et al.  On Improving Diagnostic Test Generation for Scan Chain Failures , 2009, 2009 Asian Test Symposium.

[31]  Yu Hu,et al.  Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method , 2010, 2010 19th IEEE Asian Test Symposium.

[32]  Jun Matsushima,et al.  A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule , 2012, TODE.

[33]  Chien-Mo James Li,et al.  Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis , 2012, IEEE Transactions on Computers.

[34]  Michael S. Hsiao,et al.  A SMT-based diagnostic test generation method for combinational circuits , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

[35]  Udo Mahlstedt,et al.  DIATEST: a fast diagnostic test pattern generator for combinational circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[36]  Spyros Tragoudas,et al.  A Novel Test Generation Methodology for Adaptive Diagnosis , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[37]  Irith Pomeranz,et al.  Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Dong Xiang,et al.  Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects , 2011, 2011 Asian Test Symposium.

[39]  Yu Hu,et al.  Diagnosis and Layout Aware (DLA) scan chain stitching , 2013, 2013 IEEE International Test Conference (ITC).

[40]  Irith Pomeranz Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults , 2011, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing.

[41]  Yu Huang,et al.  Distributed dynamic partitioning based diagnosis of scan chain , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[42]  Irith Pomeranz,et al.  A diagnostic test generation procedure for synchronous sequential circuits based on test elimination , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[43]  Hiroshi Takahashi,et al.  Diagnostic test generation for transition faults using a stuck-at ATPG tool , 2009, 2009 International Test Conference.

[44]  Yu Huang Dynamic Learning Based Scan Chain Diagnosis , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.