Low-frequency noise of integrated polysilicon resistors

This paper presents an analytical first principle model for the low-frequency noise current of polysilicon layers used as resistors in analog CMOS applications. The observed noise is much higher than predicted by the models mostly used in circuit simulation. The dependence on specific processing parameters such as doping or deposition techniques are investigated and explained. The model is confirmed by measurement of deviations in the flicker noise behavior of small size resistors. Guidelines for analog circuit design and a noise model for circuit simulation are presented.

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