Exact calculation of synchronization sequences based on binary decision diagrams

A synchronization sequence for a synchronous design D is a sequence of primary input vectors which when applied to any initial state of D will drive D to a single state, called a reset state. The authors present efficient methods based upon the universal alignment theorem and binary decision diagrams to compute a synchronization sequence, to compute a tight lower bound for the length of such a sequence, and to check that an initial state given in the specification is a reset state. It was shown in the experiments that the proposed method can handle fairly large circuits and the length of the actual synchronization sequence computed is quite close to the lower bound.<<ETX>>

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