Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect

Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI), triple well, and guard rings. Although SOI technology is widely reported to be immune to SEL, conventional pnpn latchup can occur and has been observed in non-dielectrically isolated SOI processes. Triple well technologies are shown to be more robust against SEL than dual well technologies under all conditions used in this study, suggesting that the introduction of a deep N-well is an excellent zero-area-penalty hardening strategy. A single guard ring is shown to be sufficient for SEL immunity in the 180 nm CMOS technology investigated, and is likely sufficient for more modern CMOS technologies. After triggering latchup in a certain pnpn region, latchup was observed to spread to neighboring pnpn regions, which then infected other more distant regions until it had spread over a total distance of 700 micrometers. We discuss the physical mechanism of this latchup domino effect and its implications for device characterization and hardness assurance.

[1]  R. D. Schrimpf,et al.  SEL-Sensitive Area Mapping and the Effects of Reflection and Diffraction From Metal Lines on Laser SEE Testing , 2013, IEEE Transactions on Nuclear Science.

[2]  B. L. Bhuva,et al.  Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs , 2011, IEEE Transactions on Nuclear Science.

[3]  L. W. Massengill,et al.  Impact of Well Structure on Single-Event Well Potential Modulation in Bulk CMOS , 2011, IEEE Transactions on Nuclear Science.

[4]  Scott Jordan,et al.  Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications , 2010, Security + Defence.

[5]  A. Wilson,et al.  Radiation and Reliability Characterization of a Multiplexer Family Using a 0.35µm Triple-Well CMOS Technology , 2010, 2011 IEEE Radiation Effects Data Workshop.

[6]  A. N. Smirnov,et al.  ANITA — a new neutron facility for accelerated SEE testing at the svedberg laboratory , 2009, 2009 IEEE International Reliability Physics Symposium.

[7]  G. Gasiot,et al.  Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering , 2007, IEEE Transactions on Nuclear Science.

[8]  H. Puchner,et al.  Neutron Induced Micro SEL Events in COTS SRAM Devices , 2007, 2007 IEEE Radiation Effects Data Workshop.

[9]  Steven H. Voldman,et al.  Guard rings : Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology , 2006 .

[10]  H. Puchner,et al.  Elimination of Single Event Latchup in 90nm SRAM Technologies , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[11]  K. Chatty,et al.  Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[12]  E. Gebreselasie,et al.  Latchup in merged triple well structure , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[13]  S.H. Voldman,et al.  Latchup and the domino effect , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[14]  C. Duvvury,et al.  Latch-up in 65nm CMOS technology: a scaling perspective , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[15]  H. Puchner,et al.  Alpha-particle SEU performance of SRAM with triple well , 2004, IEEE Transactions on Nuclear Science.

[16]  D. McMorrow,et al.  Demonstration of single-event effects induced by through-wafer two-photon absorption , 2004, IEEE Transactions on Nuclear Science.

[17]  H.H.K. Tang,et al.  Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground , 2004, IEEE Transactions on Nuclear Science.

[18]  Franco Stellari,et al.  Optical and electrical testing of latchup in I/O interface circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[19]  P. Dodd,et al.  Radiation effects in SOI technologies , 2003 .

[20]  A. Johnston,et al.  Latent damage in CMOS devices from single-event latchup , 2002 .

[21]  D. S. Walsh,et al.  Single-event upset and snapback in silicon-on-insulator devices and integrated circuits , 2000 .

[22]  T. Scott,et al.  Application of a pulsed laser for evaluation and optimization of SEU-hard designs [CMOS] , 1999 .

[23]  D. G. Mavis,et al.  Employing radiation hardness by design techniques with commercial integrated circuit processes , 1997, 16th DASC. AIAA/IEEE Digital Avionics Systems Conference. Reflections to the Future. Proceedings.

[24]  J. Barak,et al.  Microbeam mapping of single event latchups and single event upsets in CMOS SRAMs , 1997, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294).

[25]  Larry D. Edmonds,et al.  Charge collection from ion tracks in simple EPI diodes , 1997 .

[26]  L. Rubin,et al.  Buried layer/connecting layer high energy implantation for improved CMOS latch-up , 1996, Proceedings of 11th International Conference on Ion Implantation Technology.

[27]  Allan H. Johnston,et al.  The influence of VLSI technology evolution on radiation-induced latchup in space systems , 1996 .

[28]  G. Bruguier,et al.  Single particle-induced latchup , 1996 .

[29]  O. Musseau.  Single-event effects in SOI technologies and devices , 1996 .

[30]  Stephen LaLumondiere,et al.  Correlation of picosecond laser-induced latchup and energetic particle-induced latchup in CMOS test structures , 1995 .

[31]  S. Buchner,et al.  Critical evaluation of the pulsed laser method for single event effects testing and fundamental studies , 1994 .

[32]  W. Muth,et al.  Matrix method for latch-up free demonstration in a triple-well bulk-silicon technology , 1991, RADECS 91 First European Conference on Radiation and its Effects on Devices and Systems.

[33]  J. Quincke,et al.  Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention , 1990, International Conference on Microelectronic Test Structures.

[34]  R. Koga,et al.  Heavy ion induced snapback in CMOS devices , 1989 .

[35]  Hsiao-Yi Lin,et al.  Improvement of CMOS latch-up immunity using a high energy implanted buried layer , 1989 .

[36]  Ronald R. Troutman,et al.  Latchup in CMOS Technology: The Problem and Its Cure , 1986 .

[37]  Neeraj Khurana,et al.  Pulsed Infra-Red Microscopy for Debugging Latch-Up on CMOS Products , 1984, 22nd International Reliability Physics Symposium.

[38]  Nathaniel Anson Dodds,et al.  Single event latchup: Hardening strategies, triggering mechanisms, and testing considerations , 2012 .

[39]  Sylvain Clerc,et al.  A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling , 2010, IEEE Transactions on Nuclear Science.

[40]  M. Baze,et al.  Laser-Induced Latchup Screening and Mitigation in CMOS Devices , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[41]  L. Chan,et al.  Superior latch-up resistance of high dose, high energy implanted p/sup +/ buried layers , 1999, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).

[42]  Ira H Leventhal,et al.  Comparison of DC latchup characterization techniques for CMOS technology , 1984 .

[43]  A. Ochoa,et al.  Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices , 1983, IEEE Transactions on Nuclear Science.