Design and analysis of a high-speed comparator

This paper presents the design and analysis of an ultra high-speed bipolar comparator based on master-slave architecture. The comparator can be used for very high speed data converters design. Master-slave structure is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-/spl mu/m SiGe BiCMOS process, the comparator consumes approximately 70 mW with sampling speed of 16 GHz and resolvable minimum input voltage of 8 mV peak-to-peak.

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