InP DHBT IC Technology with Implanted Collector Pedestal and Electroplated Device Contacts

The authors report an InP DHBT IC technology that incorporates an ion implanted N+ collector-pedestal for collector-base capacitance (C cb) reduction. The technology utilizes electroplating processes and sidewall spacers to form a high yield self-aligned base-emitter junction. Devices with 0.4 mum emitter junction widths demonstrate peak ft and fmax values of over 370 GHz. The devices demonstrate a ~35% reduction in Ccb versus HBTs with the same device footprint fabricated without a collector pedestal. A current mode logic (CML) divide-by-two circuit demonstrated a maximum operating frequency of 128 GHz, a -20% improvement versus the same design realized in a non-collector-pedestal process

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