Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling
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Kees G. W. Goossens | Benny Akesson | Karthik Chandrasekar | Sven Goossens | K. Goossens | K. Chandrasekar | Sven Goossens | B. Akesson
[1] Onur Mutlu,et al. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems , 2008, 2008 International Symposium on Computer Architecture.
[2] Tomas Henriksson,et al. Heterogeneous multi-core platform for consumer multimedia applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[3] Kees G. W. Goossens,et al. Architectures and modeling of predictable memory controllers for improved system integration , 2011, 2011 Design, Automation & Test in Europe.
[4] Edward A. Lee,et al. PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[5] Christoforos E. Kozyrakis,et al. Towards energy-proportional datacenter memory with mobile DRAM , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[6] Kees G. W. Goossens,et al. Architecture and optimal configuration of a real-time multi-channel memory controller , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[7] Kees G. W. Goossens,et al. Memory-map selection for firm real-time SDRAM controllers , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] B. Loop,et al. An analytical study of DRAM power consumption across memory technologies , 2011, 2011 International Conference on Energy Aware Computing.
[9] Björn Andersson,et al. Bounding memory interference delay in COTS-based multi-core systems , 2014, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).
[10] Pieter van der Wolf,et al. SoC infrastructures for predictable system integration , 2011, 2011 Design, Automation & Test in Europe.
[11] Kees G. W. Goossens,et al. Automatic Generation of Efficient Predictable Memory Patterns , 2011, 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications.
[12] Kees Goossens,et al. Memory Controllers for Real-Time Embedded Systems , 2012 .
[13] Kees Goossens,et al. Power/Performance Trade-Offs , 2016 .
[14] Karthik Chandrasekar,et al. High-Level Power Estimation and Optimization of DRAMs , 2014 .
[15] Kees Goossens,et al. Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems , 2011 .
[16] Kees G. W. Goossens,et al. Classification and Analysis of Predictable Memory Patterns , 2010, 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications.
[17] Norbert Wehn,et al. Towards variation-aware system-level power estimation of DRAMs: An empirical approach , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[18] Pieter van der Wolf,et al. Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach , 2008, 2008 Euromicro Conference on Real-Time Systems.
[19] George A. Constantinides,et al. Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search , 2009, 2009 International Conference on Field-Programmable Technology.
[20] Alois Knoll,et al. Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[21] Sally A. McKee,et al. Reflections on the memory wall , 2004, CF '04.
[22] Rodolfo Pellizzoni,et al. A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems , 2014, 2014 26th Euromicro Conference on Real-Time Systems.
[23] Kees G. W. Goossens,et al. Run-time power-down strategies for real-time SDRAM memory controllers , 2012, DAC Design Automation Conference 2012.
[24] Onur Mutlu,et al. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach , 2008, 2008 International Symposium on Computer Architecture.
[25] Francisco J. Cazorla,et al. Timing effects of DDR memory systems in hard real-time multicore architectures , 2013, ACM Trans. Embed. Comput. Syst..
[26] Bruce Jacob,et al. Memory Systems: Cache, DRAM, Disk , 2007 .
[27] Artur Burchard,et al. A real-time streaming memory controller , 2005, Design, Automation and Test in Europe.
[28] Lizy Kurian John,et al. The virtual write queue: coordinating DRAM and last-level cache policies , 2010, ISCA.
[29] Alois Knoll,et al. Bounding SDRAM interference: Detailed analysis vs. latency-rate analysis , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[30] William J. Dally,et al. Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[31] Norbert Wehn,et al. DRAM selection and configuration for real-time mobile systems , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[32] Trevor N. Mudge,et al. A performance comparison of contemporary DRAM architectures , 1999, ISCA.
[33] Kees G. W. Goossens,et al. Improved Power Modeling of DDR SDRAMs , 2011, 2011 14th Euromicro Conference on Digital System Design.
[34] Kees G. W. Goossens,et al. Dynamic Command Scheduling for Real-Time Memory Controllers , 2014, 2014 26th Euromicro Conference on Real-Time Systems.