Automatic synthesis of reconfigurable instruction set accelerators
暂无分享,去创建一个
[1] Vivek Sarkar,et al. Baring It All to Software: Raw Machines , 1997, Computer.
[2] Michael D. Smith,et al. A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.
[3] Steven S. Muchnick,et al. Advanced Compiler Design and Implementation , 1997 .
[4] Jan Hoogerbrugge,et al. ConCISe: a compiler-driven CPLD-based instruction set accelerator , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).
[5] D. Bursky. Tool suite enables designers to craft customized embedded processors , 1999 .
[6] Viktor K. Prasanna,et al. Seeking Solutions in Configurable Computing , 1997, Computer.
[7] Bob Zeidman,et al. Designing with FPGAs and CPLDs , 2002 .
[8] Bernardo Kastrup. Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs , 1998, ArXiv.
[9] Michael J. Wirthlin,et al. The Nano Processor: a low resource reconfigurable processor , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.
[10] Ehl Emile Aarts,et al. Simulated annealing and Boltzmann machines , 2003 .
[11] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[12] John Wawrzynek,et al. Instruction-Level Parallelism for Reconfigurable Computing , 1998, FPL.
[13] Brad L. Hutchings,et al. Implementation Approaches for Reconfigurable Logic Applications , 1995, FPL.
[14] John Wawrzynek,et al. Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[15] Orlando Moreira,et al. A novel approach to minimising the logic of combinatorial multiplexing circuits in product-term-based hardware , 2000, Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future.
[16] Bernardo Kastrup,et al. Seeking (the right) Problems for the Solutions of Reconfigurable Computing , 1999, FPL.
[17] Carl Ebeling,et al. Specifying and compiling applications for RaPiD , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[18] Scott Hauck,et al. The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.
[19] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Re-configurable Architecture , 2000 .
[20] Markus Weinhardt. Compilation and Pipeline Synthesis for Reconfigurable Architectures , 1997 .
[21] Sergei Sawitzki,et al. Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays , 1998, FPL.
[22] Harvey F. Silverman,et al. Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.
[23] Bruce Schneier,et al. Applied cryptography : protocols, algorithms, and source codein C , 1996 .
[24] Orlando Moreira,et al. Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis , 2000, FPL.
[25] Rahul Razdan,et al. PRISC: programmable reduced instruction set computers , 1994 .
[26] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[27] Markus Weinhardt,et al. Integer Programming for Partitioning in Software Oriented Codesign , 1995, FPL.
[28] Carl Ebeling,et al. RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.
[29] P. Ashar,et al. Sequential Logic Synthesis , 1991 .
[30] Steve Rogers,et al. Adaptive Filter Theory , 1996 .
[31] Nikolaus Lange,et al. Single-Chip Implementation of a Cryptosystem for Financial Applications , 1997, Financial Cryptography.
[32] G. D. La Hei,et al. TriMedia CPU64 design space exploration , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).
[33] André DeHon,et al. The Density Advantage of Configurable Computing , 2000, Computer.
[34] A. van der Werf. Processing unit design , 1998 .
[35] David A. Patterson,et al. Computer Organization & Design: The Hardware/Software Interface , 1993 .
[36] John Wawrzynek,et al. Fast module mapping and placement for datapaths in FPGAs , 1998, FPGA '98.
[37] Peter M. Athanas,et al. Colt: an experiment in wormhole run-time reconfiguration , 1996, Other Conferences.
[38] André DeHon,et al. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[39] Michael J. Wirthlin,et al. DISC: the dynamic instruction set computer , 1995, Optics East.
[40] Carl Ebeling,et al. Configurable computing: the catalyst for high-performance architectures , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.
[41] Michael D. Smith,et al. PRISC software acceleration techniques , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[42] Laura Pozzi. Methodologies for the Design of Application-Specific Reconfigurable VLIW Processors , 2000 .
[43] Geoffrey E. Hinton,et al. Learning internal representations by error propagation , 1986 .
[44] André DeHon,et al. Reconfigurable architectures for general-purpose computing , 1996 .