Generating Fast Multipliers Using Clever Circuits

New insights into the general structure of partial product reduction trees are combined with the notion of clever circuits to give a novel method of writing simple but flexible and highly parameterised data-path generators.

[1]  Vojin G. Oklobdzija,et al.  A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.

[2]  Henrik Eriksson.  Efficient Implementation and Analysis of CMOS Arithmetic Circuits , 2003 .

[3]  William P. Marnane,et al.  A regular parallel multiplier which utilizes multiple carry-propagate adders , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[4]  D. Kroening,et al.  Formal Verification of a Basic Circuits Library , 2001 .

[5]  Robert K. Brayton,et al.  A timing-driven module-based chip design flow , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  F. Jutand,et al.  "Overturned-Stairs" Adder Trees and Multiplier Design , 1992, IEEE Trans. Computers.

[7]  H. Al-Twaijry,et al.  An algorithmic approach to building datapath multipliers using (3,2) counters , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

[8]  J. Vuillemin,et al.  Recursive implementation of optimal time VLSi integer multipliers , 1984 .

[9]  Bishop Brock,et al.  The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor , 1997, Formal Methods Syst. Des..

[10]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[11]  Mary Sheeran,et al.  Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular , 2003, CHARME.

[12]  Taewhan Kim,et al.  Synthesis of arithmetic circuits considering layout effects , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  R. Ravi,et al.  Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.

[14]  George J. Milne,et al.  Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.