Mu-GSIM: A mutation testing simulator on GPUs

Graphics Processing Units (GPUs) have recently gained widespread usage as an advanced parallel platform for accelerating compute intensive applications. The maturity of programming interfaces and the improved programmability of GPUs have enabled the development of parallel algorithms that leverage the wealth of compute power provided by them. In this paper, we present μ-GSIM, a GPU-based simulation tool that leverages the inherent bit parallelism of GPUs for accelerating simulations of mutated digital circuits. We propose an efficient mapping of multiple mutated circuits on the GPU's device memory, where we exploit as much data parallelism as possible so our GPU simulation kernel can achieve maximal performance by operating on independent data. Results show that with the largest ITC'99 circuit benchmarks we were able to achieve a 60% decrease in memory usage while gaining a 5.4× increase in simulation performance. Additionally, we demonstrated a speedup of at least 95× against a commercial event-driven simulation tool running on a conventional processor. This is beneficial in the quest for improving test quality.

[1]  J. Offutt,et al.  Mutation testing implements grammar-based testing , 2006, Second Workshop on Mutation Analysis (Mutation 2006 - ISSRE Workshops 2006).

[2]  Michael S. Hsiao,et al.  3-D Parallel Fault Simulation With GPGPU , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Franco Fummi,et al.  Testbench Qualification of SystemC TLM Protocols through Mutation Analysis , 2014, IEEE Transactions on Computers.

[4]  Hans-Joachim Wunderlich,et al.  Efficient fault simulation on many-core processors , 2010, Design Automation Conference.

[5]  Sara Vinco,et al.  SystemC simulation on GP-GPUs: CUDA vs. OpenCL , 2012, CODES+ISSS '12.

[6]  Sunil P. Khatri,et al.  Introduction to GPU programming for EDA , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[7]  Magdy S. Abadir,et al.  Logic design verification via test generation , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  John D. Owens,et al.  GPU Computing , 2008, Proceedings of the IEEE.

[9]  Valeria Bertacco,et al.  Gate-Level Simulation with GPU Computing , 2011, TODE.

[10]  Arturo González-Escribano,et al.  Using Fermi Architecture Knowledge to Speed up CUDA and OpenCL Programs , 2012, 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications.

[11]  Luca P. Carloni,et al.  Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , 2012 .

[12]  Alper Sen,et al.  Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units , 2011, International Journal of Parallel Programming.

[13]  Alper Sen,et al.  Parallel Cycle Based Logic Simulation Using Graphics Processing Units , 2010, 2010 Ninth International Symposium on Parallel and Distributed Computing.

[14]  Emmett Kilgariff,et al.  Fermi GF100 GPU Architecture , 2011, IEEE Micro.

[15]  Kwang-Ting Cheng,et al.  RTL Error Diagnosis Using a Word-Level SAT-Solver , 2008, 2008 IEEE International Test Conference.

[16]  Alper Sen,et al.  Generation of TLM testbenches using mutation testing , 2012, CODES+ISSS '12.

[17]  Sunil P. Khatri,et al.  Towards acceleration of fault simulation using Graphics Processing Units , 2008, 2008 45th ACM/IEEE Design Automation Conference.