Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis

Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consideration of design performance. Timing-driven mode requires that a designer specify performance constraints and then produces a performance-optimized layout solution. The task of generating constraints is burdensome since design performance is difficult to gauge at the pre-layout stage and the relationship between the constraints supplied and tool execution time is unpredictable. In this paper, we propose a new mode for layout tools, called “automatic timing-driven” mode that produces a performance-optimized layout, without requiring any constraint specification. A key feature of this mode is a novel and practical method for automatic constraint generation that creates constraints that result in predictable and controlled layout execution time. The automatic constraint generation approach has been integrated into commercial FPGA layout tools and tuned to provide layouts having 28% better performance than non-timing-driven mode, on average. Results show that the ratio of the automatic to non-timing-driven layout execution time is consistent and predictable across a suite of designs.