Performance and reliability driven clock scheduling of sequential logic circuits

It is known that the clock-period in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to find the minimum clock-period of a circuit whose signal propagation delays are given. Experimental results on LGSynth93 benchmarks show that this technique achieves as much as about 16% reduction of clock-period compared with the conventional maximum signal delay based methods. An application of this technique to improve the reliability of circuits is considered.

[1]  R.-S. Tsay,et al.  Exact zero skew , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Sachin S. Sapatnekar,et al.  A graph-theoretic approach to clock skew optimization , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  Masato Edahiro,et al.  A Clustering-Based Optimization Algorithm in Zero-Skew Routings , 1993, 30th ACM/IEEE Design Automation Conference.

[5]  Kunle Olukotun,et al.  Analysis and design of latch-controlled synchronous digital circuits , 1990, DAC '90.

[6]  Richard M. Karp,et al.  A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..

[7]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[8]  E. Kuh,et al.  Clock routing for high-performance ICs , 1990, 27th ACM/IEEE Design Automation Conference.

[9]  Marios C. Papaefthymiou.  Understanding retiming through maximum average-weight cycles , 1991, SPAA '91.

[10]  Sachin S. Sapatnekar Rahul B. Deokar.  A Fresh Look at Retiming via Clock Skew Optimization , 1995, 32nd Design Automation Conference.

[11]  Lawrence R. Rabiner,et al.  Combinatorial optimization:Algorithms and complexity , 1984 .

[12]  Maciej J. Ciesielski,et al.  Placement for clock period minimization with multiple wave propagation , 1991, 28th ACM/IEEE Design Automation Conference.

[13]  M. R. Rao,et al.  Combinatorial Optimization , 1992, NATO ASI Series.

[14]  Eby G. Friedman,et al.  Circuit synthesis of clock distribution networks based on non-zero clock skew , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.