Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs

This paper introduces a methodology for prototyping globally asynchronous locally synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19,6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.

[1]  Johnny Öberg,et al.  Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.

[2]  Peter Y. K. Cheung,et al.  Asynchronous wrapper for heterogeneous systems , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[3]  Peter Robinson,et al.  Point to point GALS interconnect , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[4]  Peter Robinson,et al.  An on-chip dynamically recalibrated delay line for embedded self-timed systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[5]  Carl Ebeling,et al.  MONTAGNE: An FPL for Synchronous and Asynchronous Circuits , 1992, FPL.

[6]  Robert Payne,et al.  Self-timed field programmmable gate array architectures , 1997 .

[7]  Peter Y. K. Cheung,et al.  Globally Asynchronous Locally Synchronous FPGA Architectures , 2003, FPL.

[8]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[9]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[10]  Peter Thomas,et al.  An architecture for asynchronous FPGAs , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[11]  Stephen B. Wicker,et al.  Reed-Solomon Codes and Their Applications , 1999 .

[12]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[13]  Kenneth Y. Yun,et al.  Pausible clocking-based heterogeneous systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .