Generalized Multiway Branch Unit for VLIW Microprocessors

VLIW processors use multiway branch instructions to achieve high-speed, parallel evaluation of control structures. This paper introduces a new multiway branch mechanism that allows constant-time branch-target resolution based on an arbitrary condition tree. The unique feature of this mechanism is its target selection unit, which yields a branch-target based on a set of condition bit values and a condition tree description. A representation of condition trees that results in a compact target selection unit is described, and the logic diagram of a target selection unit that provides a four-way branching is shown. Our experimental results on nontrivial integer benchmarks indicate that the proposed multiway branch unit can improve the performance of VLIW machines substantially (i.e., as much as a geometric mean of 35%), compared to using the conventional two-way branching. >

[1]  Soo-Mook Moon,et al.  Increasing Instruct ion-level Parallelism through Multi-way Branching , 1993, 1993 International Conference on Parallel Processing - ICPP'93.

[2]  Soo-Mook Moon.  Compile-time parallelization of non-numerical code: VLIW superscalar , 1993 .

[3]  Toshio Nakatani,et al.  A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture , 1990 .

[4]  B. Ramakrishna Rau,et al.  Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.

[5]  Joseph A. Fisher,et al.  2n-way jump microinstruction hardware and an effective instruction binding method , 1980, SIGM.

[6]  Kemal Ebcioglu,et al.  An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.

[7]  Michael Rodeh,et al.  Global instruction scheduling for superscalar machines , 1991, PLDI '91.

[8]  Alexandru Nicolau,et al.  Efficient hardware for multiway jumps and pre-fetches , 1985, MICRO 18.

[9]  Toshio Nakatani,et al.  Making Compaction-Based Parallelization Affordable , 1993, IEEE Trans. Parallel Distributed Syst..

[10]  John R. Ellis,et al.  Bulldog: A Compiler for VLIW Architectures , 1986 .

[11]  Soo-Mook Moon,et al.  Hardware implementation of a general multi-way jump mechanism , 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.

[12]  Michael D. Smith,et al.  Efficient superscalar performance through boosting , 1992, ASPLOS V.

[13]  S. McFarling,et al.  Reducing the cost of branches , 1986, ISCA '86.

[14]  Alexander Aiken,et al.  A Development Environment for Horizontal Microcode , 1986, IEEE Trans. Software Eng..