Asymmetric Multilevel Converter for High Resolution Voltage Phasor Generation

Recent publications on so called multilevel inverters deal with series connected cells, mainly developed for the increase of the output-voltage magnitude, in order to meet the classical design levels of medium size motors in the lower megawatt power range [1], [2], [3], [4]. In all well-known multilevel topologies, generally a regular or symmetric voltage share over all partial sources has been chosen, with as main goal a better use of the individual silicon devices regarding the possible blocking properties. The definition of the resulting output voltage has generally been sufficient due to the high number of series connected cells. In the proposed solution, the main efforts are set to the aspect of getting a higher resolution of the voltage phasor, in relation with the use of motors with strongly reduced leakage inductances. Together with the specification of a limited current harmonic content, even the frequency of the fundamental component is an important parameter. One application field will be the variable speed drives for ultra-speed kinetic energy storage.