RPSim: A Rapid Prototyping Full-System Simulator for SoC Software Development

Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform for SoC software development should be available as soon as possible after hardware design. However, state-of-the-art SoC simulators lack the support for fast integration of IP core and require time-consuming compiler chain modifications for new instructions. In this paper, we present Prism, an extensible and easy-to-use full-system SoC simulation platform for SoC software development. Two mechanisms are designed and implemented to support fast prototyping for new IP core simulation or new instruction extension without compiler tool chain modifications. First, a hardware and software hybrid mechanism is proposed for IP core fast prototyping. A seamless interface is used to eliminate the differences among IP cores. Second, a configurable library mechanism is designed for new instruction extension. Register dependence can be maintained for detailed timing simulation without compiler tool chain modification. In such a design, the major effort for extension is to specify the elaborate common customization interface. Experimental results show these mechanisms only involve about 0.36% runtime overhead. Based on RPSim, a graduate student only needs write about 40 lines of code and takes less than half an hour to extend a new IP core simulation in RPSim.

[1]  Zhenman Fang,et al.  Transformer: A functional-driven cycle-accurate multicore simulator , 2012, DAC Design Automation Conference 2012.

[2]  Shunfei Chen,et al.  MARSS: A full system simulator for multicore x86 CPUs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Hui Zeng,et al.  MPTLsim: A simulator for X86 multicore processors , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[4]  Björn Franke,et al.  Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems , 2007, LCTES '07.

[5]  Karthikeyan Sankaralingam,et al.  Design, integration and implementation of the DySER hardware accelerator into OpenSPARC , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[6]  Björn Franke,et al.  Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation , 2012, LCTES 2012.

[7]  Francesco Robino,et al.  NoC System Generator : a Tool for Fast Prototyping of Multi-Core Systems on FPGAs , 2013 .

[8]  Luca Fossati,et al.  IP-SOC 2010 TLM 2 . 0 STANDARD INTO ACTION : DESIGNING EFFICIENT PROCESSOR SIMULATOR , 2010 .

[9]  Antonio Martínez-Álvarez,et al.  Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[10]  David I. August,et al.  Exploiting parallelism and structure to accelerate the simulation of chip multi-processors , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[11]  Kim Hazelwood,et al.  Zsim : A Fast Architectural Simulator for ISA Design-Space Exploration , 2011 .

[12]  Matt T. Yourst PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator , 2007, 2007 IEEE International Symposium on Performance Analysis of Systems & Software.

[13]  Rodolfo Azevedo,et al.  The ArchC Architecture Description Language and Tools , 2005, International Journal of Parallel Programming.

[14]  Fabrice Bellard,et al.  QEMU, a Fast and Portable Dynamic Translator , 2005, USENIX ATC, FREENIX Track.