Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells
暂无分享,去创建一个
F. Saigné | V. Pouget | S. Guagliardo | F. Saigné | Y. Aguiar | F. Wrobel | S. Guagliardo | J. Autran | P. Leroux | A. Touboul | V. Pouget | Y.Q. Aguiar | F. Wrobel | J.-L. Autran | P. Leroux | A.D. Touboul
[1] J. von Neumann,et al. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[2] J. F. Leavy,et al. Radiation-Induced Integrated Circuit Latchup , 1969 .
[3] J. V. Osborn,et al. Total dose hardness of three commercial CMOS microelectronics foundries , 1997, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294).
[4] J. V. Osborn,et al. Total dose hardness of three commercial CMOS microelectronics foundries , 1997 .
[5] Olivier Coudert,et al. Gate sizing for constrained delay/power/area optimization , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[6] Vivek De,et al. A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[7] Federico Faccio,et al. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects , 1999 .
[8] M. Baze,et al. A digital CMOS design technique for SEU hardening , 2000 .
[9] R. Koga,et al. Application of hardness-by-design methodology to radiation-tolerant ASIC technologies , 2000 .
[10] Stephen LaLumondiere,et al. A single event latchup suppression technique for COTS CMOS ICs , 2003 .
[11] Shekhar Y. Borkar,et al. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.
[12] F. Wrobel,et al. Criterion for SEU occurrence in SRAM deduced from circuit and device Simulations in case of neutron-induced SER , 2005, IEEE Transactions on Nuclear Science.
[13] R.C. Baumann,et al. Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.
[14] Kartik Mohanram,et al. Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Paul D. Franzon,et al. FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).
[16] R. Lacoe. Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology , 2008, IEEE Transactions on Nuclear Science.
[17] D. Munteanu,et al. Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.
[18] F. Wrobel,et al. Prediction of Multiple Cell Upset Induced by Heavy Ions in a 90 nm Bulk SRAM , 2009, IEEE Transactions on Nuclear Science.
[19] M. Cabanas-Holmen,et al. Heavy Ion and High Energy Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR Gates , 2009, IEEE Transactions on Nuclear Science.
[20] P E Dodd,et al. Current and Future Challenges in Radiation Effects on CMOS Electronics , 2010, IEEE Transactions on Nuclear Science.
[21] R A Reed,et al. SEU Prediction From SET Modeling Using Multi-Node Collection in Bulk Transistors and SRAMs Down to the 65 nm Technology Node , 2011, IEEE Transactions on Nuclear Science.
[22] P. Marshall,et al. 32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches , 2011, IEEE Transactions on Nuclear Science.
[23] Guilherme Flach,et al. Gate Sizing Minimizing Delay and Area , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.
[24] Frédéric Saigné,et al. MC-ORACLE: A tool for predicting Soft Error Rate , 2011, Comput. Phys. Commun..
[25] Luis Entrena,et al. Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects , 2012, IEEE Transactions on Nuclear Science.
[26] P. E. Dodd,et al. Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.
[27] Shuming Chen,et al. Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor , 2013, IEEE Transactions on Device and Materials Reliability.
[28] B. L. Bhuva,et al. Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty , 2013, IEEE Transactions on Nuclear Science.
[29] William H. Robinson,et al. Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.
[30] Shuming Chen,et al. A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits , 2014, IEEE Transactions on Device and Materials Reliability.
[31] J. S. Kauppila,et al. Utilizing device stacking for area efficient hardened SOI flip-flop designs , 2014, 2014 IEEE International Reliability Physics Symposium.
[32] L. Dilillo,et al. Determining Realistic Parameters for the Double Exponential Law that Models Transient Current Pulses , 2014, IEEE Transactions on Nuclear Science.
[33] Guillaume Hubert,et al. Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation , 2015, Integr..
[34] J. S. Kauppila,et al. An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology , 2016, IEEE Transactions on Nuclear Science.
[35] Eduardo Chielle,et al. Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques , 2016, IEEE Transactions on Nuclear Science.
[36] Fernanda Gusmão de Lima Kastensmidt,et al. Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology , 2017, Microelectron. Reliab..
[37] J.-L. Autran,et al. Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions , 2018, Microelectron. Reliab..
[38] F. Wrobel,et al. Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity , 2019, IEEE Transactions on Nuclear Science.