论文信息 - Extracting Exact Time Bounds from Logical Proofs

Extracting Exact Time Bounds from Logical Proofs

Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.

[1] Michael Zakharyaschev,et al. Modal Logic , 1997, Oxford logic guides.

[2] Michael Mendler,et al. Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic , 2000, Formal Methods Syst. Des..

[3] Michael Mendler. A Timing Refinement of Intuitionistic Proofs and its Application to the Timing Analysis of Combinational Circuits , 1996, TABLEAUX.

[4] Richmond H. Thomason,et al. A semantical study of constructible falsity , 1969 .

[5] Sharad Malik. Analysis of cyclic combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6] D. Prawitz. Natural Deduction: A Proof-Theoretical Study , 1965 .

[7] Pierangelo Miglioli,et al. Some Results on Intermediate Constructive Logics , 1989, Notre Dame J. Formal Log..

[8] Michael Mendler. Characterising Combinational Timing Analyses in Intuitionistic Modal Logic , 2000, Log. J. IGPL.

[9] Wentai Liu,et al. Circuit delay calculation considering data dependent delays , 1994, Integr..

[10] Michael Yoeli,et al. Ternary Simulation of Binary Gate Networks , 1977 .

[11] Pierangelo Miglioli,et al. A Constructivism Based on Classical Truth , 1988, Notre Dame J. Formal Log..

[12] Nils Klarlund,et al. Automata based symbolic reasoning in hardware verification , 1998, FM-Trends 1998.