Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective

System on chip (SoC) contains multiple intellectual properties (IPs) that work in different clock domains. Several of those IPs may even have multiple clock domains within itself and provided to SoC designers as hard IPs. Different clock domain crossing (CDC) techniques are used to communicate among different clock domains. First In First Out (FIFO) buffers are part of several CDC circuits. This research explores the possible security vulnerabilities of such SoCs in the event of compromised security in FIFO buffers. We investigated few catastrophic possibilities of hardware Trojans in FIFO buffers and discussed its potential consequences. Testing the design using random bit generation showed that the triggering probabilities of such Trojans are less than 8/1000. Our synthesis results show that majority of these Trojans require minimal area and frequency overhead, in the range of .8% and 1%, respectively, if FIFO occupies 10% space of the IP.