Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64 dB is achievable at an input signal frequency of 10 kHz and a sampling clock of 2 MHz. Measurements of the test chip confirmed that the measurements match the analyses. key words: TDC, FSO, jitter, design methodology

[1]  SeongHwan Cho,et al.  A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register , 2014, IEEE Journal of Solid-State Circuits.

[2]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.

[3]  SeongHwan Cho,et al.  A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register , 2013, 2013 Symposium on VLSI Circuits.

[4]  Shintaro Izumi,et al.  A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator , 2012, 10th IEEE International NEWCAS Conference.

[5]  Shingo Mandai,et al.  A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imaging , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[6]  Kunihiro Asada,et al.  A stochastic sampling time-to-digital converter with tunable 180–770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[7]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[8]  Shintaro Izumi,et al.  A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops , 2013, IEICE Trans. Electron..

[9]  Jae-Yoon Sim,et al.  A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS , 2012, IEEE Journal of Solid-State Circuits.

[10]  Byungsub Kim,et al.  A fractionally spaced linear receive equalizer with voltage-to-time conversion , 2009, 2009 Symposium on VLSI Circuits.

[11]  SeongHwan Cho,et al.  A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier , 2012, 2012 Symposium on VLSI Circuits (VLSIC).