An empirical study of crosstalk in VDSM technologies

We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the crosstalk effects in VLSI circuits. As example of these observations, we report that the combination of one crosstalk event at some site and another crosstalk event at a different site in the transitive fan-out of the first site may cause a slowdown or speedup of the circuit by an amount that can significantly exceed the sum of crosstalk effects caused by each site in isolation. As another example, we report that the common assumption that zero skew between the input transitions of aggressor and victim lines causes the worst case crosstalk effect is not always valid, and therefore, optimization or test based on such an assumption may be invalid. We also demonstrate the non-monotone behavior of the crosstalk effect with respect to the skew between the input transition of aggressor and victim lines. This work provides a first step toward the development of a new framework for timing analysis and test development in the presence of crosstalk events.

[1]  Malgorzata Marek-Sadowska,et al.  Modeling Crosstalk Induced Delay , 2003, ISQED.

[2]  Rajendran Panda,et al.  Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[3]  S.K. Gupta,et al.  Accurate and efficient static timing analysis with crosstalk , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[4]  Kurt Keutzer,et al.  Switching window computation for static timing analysis in presence of crosstalk noise , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[5]  Jason Cong,et al.  Improved crosstalk modeling for noise constrained interconnect optimization , 2001, ASP-DAC '01.

[6]  Yu Cao,et al.  Efficient generation of delay change curves for noise-aware static timing analysis , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[7]  Shahin Nazarian,et al.  Analyzing crosstalk in the presence of weak bridge defects , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[8]  Chandra Tirumurti,et al.  On Modeling Cross-Talk Faults , 2003 .

[9]  Melvin A. Breuer,et al.  Test generation for crosstalk-induced delay in integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Xiaole Xu,et al.  An approach to the analysis and detection of crosstalk faults in digital VLSI circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  David Blaauw,et al.  Driver modeling and alignment for worst-case delay noise , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Massoud Pedram,et al.  Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[13]  Melvin A. Breuer,et al.  Analytical models for crosstalk excitation and propagation in VLSI circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Chandra Tirumurti,et al.  On modeling crosstalk faults , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Melvin A. Breuer,et al.  Analytic models for crosstalk delay and pulse analysis under non-ideal inputs , 1997, Proceedings International Test Conference 1997.