论文信息 - An Intelligent RAM with Serial I/Os

An Intelligent RAM with Serial I/Os

Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine family of integrated circuits provides a significant improvement in effective memory performance by using high-speed serial I/O's, many banks of memory, a low-latency, highly efficient protocol, and intelligence within the device. The first member of the family can perform 2 billion 72-bit reads per second or 1 billion read-modify-write operations per second.

[1] Said Hamdioui,et al. Yield Improvement for 3D Wafer-to-Wafer Stacked Memories , 2012, J. Electron. Test..

[2] Christoforos E. Kozyrakis,et al. A case for intelligent RAM , 1997, IEEE Micro.

[3] Tomonori Sekiguchi,et al. 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing , 2011, IEEE Journal of Solid-State Circuits.

[4] Balaram Sinharoy,et al. POWER7: IBM's next generation server processor , 2010, 2009 IEEE Hot Chips 21 Symposium (HCS).

[5] Stephan Bunse,et al. Towards 100G packet processing: Challenges and technologies , 2009 .

[6] Jae Choi,et al. A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).